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A 95.9-dB SNDR 10-kHz BW 3rd-Order VCO-Based CT ΔΣ Modulator Using a Phase-Time Two-Step Quantizer

https://doi.org/10.1109/CICC63670.2025.10983499

Li, Ken; Lee, Wei-En; Zhang, Xitie; Xie, Tian; Wang, Tzu-Han; Sathe, Visvesh; Li, Shaolan (April 2025, IEEE)

Free, publicly-accessible full text available April 13, 2026
A 50-kHz BW 92.1-dB SNDR Incremental ADC Using a Back-End Sampling Two-Step NS-SAR Architecture with Concurrent Gain-Error + Noise Suppression

https://doi.org/10.1109/CICC63670.2025.10983053

Wang, Tzu-Han; Li, Chenyang; Kang, Dong Suk; Li, Ken; Zhang, Xitie; Lee, Wei-En; Sathe, Visvesh; Li, Shaolan (April 2025, IEEE)

Free, publicly-accessible full text available April 13, 2026
An 82dB-SNDR Input-Driving-Relaxed Noise-Shaping SAR with Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping

https://doi.org/10.1109/CICC60959.2024.10528963

Xie, Tian; Li, Ken; Wang, Tzu-Han; Lee, Wei-En; Esen, Engin; Kang, Dong Suk; Li, Shaolan (April 2024, IEEE)

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VSAGE: An End-to-End Automated VCO-Based $$\Delta$$ $$\Sigma$$ ADC Generator

https://doi.org/10.1109/TVLSI.2024.3507567

Li, Ken; Xie, Tian; Wang, Tzu-Han; Li, Shaolan (January 2024, IEEE Transactions on Very Large Scale Integration (VLSI) Systems)

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